Semiconductor chip and semiconductor package

ABSTRACT

A semiconductor chip includes; an intermetal dielectric (IMD) layer on a substrate, an uppermost insulation layer on the IMD layer, the uppermost insulation layer having a dielectric constant different from a dielectric constant of the IMD layer, a metal wiring in the IMD layer, the metal wiring including a via contact and a metal pattern, a metal pad in the uppermost insulation layer, the metal pad being electrically connected to the metal wiring, and a bump pad on the metal pad. An interface portion between the IMD layer and the uppermost insulation layer is disposed at a height of a portion between an upper surface and a lower surface of an uppermost metal pattern in the IMD layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC § 119 to Korean PatentApplication No. 10-2020-0115328 filed on Sep. 9, 2020 in the KoreanIntellectual Property Office (KIPO), the subject matter of which ishereby incorporated by reference.

BACKGROUND 1. Field

Embodiments of the inventive concept relate generally to semiconductorchips and semiconductor packages including semiconductor chip(s).

2. Description of the Related Art

A semiconductor package may include a semiconductor chip disposed on apackage substrate using conductive bumps. Due to differences incoefficients of thermal expansion associated with the semiconductor chipand the package substrate, thermal stress may arise at various pointswith the semiconductor package, such as contact points of the conductivebump(s), the so-called “back end of the line” area (hereafter, BEOL),etc. For example, thermal stress may cause chip-package-interaction(CPT) defects, such as delamination and/or cracking of intermetaldielectric (IMD) layers in the BEOL.

SUMMARY

Embodiments of the inventive concept provide semiconductor chips lesssusceptible to CPI defects potentially caused by thermal stress.Embodiments of the inventive concept also provide semiconductor packagesexhibiting a reduced number of CPT defects.

According to embodiments, there is provided a semiconductor chipincluding; an intermetal dielectric (IMD) layer on a substrate, anuppermost insulation layer on the IMD layer, the uppermost insulationlayer having a dielectric constant different from a dielectric constantof the IMD layer, a metal wiring in the IMD layer, the metal wiringincluding a via contact and a metal pattern, a metal pad in theuppermost insulation layer, the metal pad being electrically connectedto the metal wiring, and a bump pad on the metal pad, wherein aninterface portion between the IMD layer and the uppermost insulationlayer is disposed at a height of a portion between an upper surface anda lower surface of an uppermost metal pattern in the IMD layer.

According to embodiments, there is provided a semiconductor chipincluding; a first intermetal dielectric (IMD) layer on a substrate, thefirst IMD layer having a first dielectric constant, a second IMD layeron the first IMD layer, the second IMD layer having a second dielectricconstant different from the first dielectric constant, a third IMD layeron the second IMD layer, the third IMD layer having a third dielectricconstant different from the second dielectric constant, an uppermostinsulation layer on the third IMD layer, the uppermost insulation layerhaving a fourth dielectric constant different from the third dielectricconstant, a first metal wiring in the first IMD layer, the first metalwiring including a first via contact and a first metal pattern, a secondmetal wiring in the second IMD layer, the second metal wiring includinga second via contact and a second metal pattern, a third metal wiring inthe third IMD layer, the third metal wiring including a third viacontact and a third metal pattern, a metal pad in the uppermostinsulation layer, the metal pad being electrically connected to thethird metal wiring, and a bump pad for forming a conductive bump on themetal pad, wherein in a first region of the substrate, an upper surfaceof the third metal pattern disposed at an uppermost portion is exposedthrough an upper surface of the third IMD layer.

According to embodiments, there is provided a semiconductor packageincluding; a package substrate, a semiconductor chip, and conductivebumps interposed between the package substrate and the semiconductorchip and electrically connecting the semiconductor chip and the packagesubstrate. The semiconductor chip includes; an intermetal dielectric(IMD) layer on a substrate, an uppermost insulation layer contacting anupper surface of the IMD layer, the uppermost insulation layer having adielectric constant different from a dielectric constant of the IMDlayer, a metal wiring in the IMD layer, the metal wiring including a viacontact and a metal pattern, a metal pad in the uppermost insulationlayer, the metal pad being electrically connected to the metal wiring,and a bump pad on the metal pad, wherein in a first region of thesubstrate, an interface portion between the IMD layer and the uppermostinsulation layer is disposed at a height of a portion between an uppersurface and a lower surface of an uppermost metal pattern in the IMDlayer.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings. FIGS. 1to 19 represent non-limiting, embodiments as described herein.

FIG. 1 is a cross-sectional view illustrating a semiconductor packageaccording to embodiments of the inventive concept;

FIG. 2 is a cross-sectional view illustrating portions of asemiconductor chip and a conductive bump according to embodiments of theinventive concept:

FIG. 3 is an enlarged view of portion ‘A’ shown in FIG. 2 ;

FIG. 4 is a cross-sectional view illustrating portions of asemiconductor chip and a conductive bump according to embodiments of theinventive concept;

FIGS. 5 and 6 are a plan view and a cross-sectional view illustratingportions of a semiconductor chip and a conductive bump according toembodiments of the inventive concept;

FIGS. 7 and 8 are a plan view and a cross-sectional view illustratingportions of a semiconductor chip and a conductive bump according toembodiments of the inventive concept;

FIG. 9 is a cross-sectional view illustrating portions of asemiconductor chip and a conductive bump according to embodiments of theinventive concept;

FIGS. 10, 11, 12, 13, 14, 15 and 16 (hereafter, “FIGS. 10 to 16 ”) arerelated cross-sectional views illustrating in one example a method formanufacturing a semiconductor chip and a conductive bump according toembodiments of the inventive concept;

FIG. 17 is a cross-sectional view illustrating portions of asemiconductor chip and a conductive bump according to embodiments of theinventive concept;

FIG. 18 is a cross-sectional view illustrating portions of asemiconductor chip and a conductive bump according to embodiments of theinventive concept; and

FIG. 19 is an enlarged view of portion ‘B’ shown in FIG. 18 .

DETAILED DESCRIPTION

Throughout the written description and drawings, like reference numbersand labels are used to denote like or similar elements and/or features.Throughout the written description certain geometric terms may be usedto highlight relative relationships between elements, components and/orfeatures with respect to certain embodiments of the inventive concept.Those skilled in the art will recognize that such geometric terms arerelative in nature, arbitrary in descriptive relationship(s) and/ordirected to aspect(s) of the illustrated embodiments. Geometric termsmay include, for example: height/width; vertical/horizontal; top/bottom;higher/lower; closer/farther, thicker/thinner; proximate/distant;above/below; under/over; upper/lower; center/side; surrounding;overlay/underlay; etc.

FIG. 1 is a cross-sectional view illustrating a semiconductor package 60according to embodiments of the inventive concept.

Referring to FIG. 1 , the semiconductor package 60 may include a packagesubstrate 10, a semiconductor chip 30, conductive bumps 20, an epoxymolding compound 40, and solder balls 50.

The semiconductor chip 30 (e.g., a memory device or a logic device) maybe disposed on an upper surface of the package substrate 10. Here, thesemiconductor device 30 may include a front end of line (FEOL) includingvarious circuits disposed on a silicon substrate, and a back end of line(BEOL) including conductive patterns (e.g., metal wirings) disposed onthe FEOL.

The BEOL may include single layer or multiple layer metal wirings formedfrom one or more conductive materials (e.g., metal(s), such as copper,aluminum, etc.). In some embodiments, the metal wirings may be formed inan intermetal dielectric (IMD) layer. The IMD layer may include siliconoxide-based materials having a low dielectric constant (low-k). In someembodiments, the IMD layer may include stacked insulation materiallayers having different dielectric constants.

The conductive bumps 20 may be interposed between the semiconductor chip30 and the package substrate 10 in such a manner to bond (electricallyconnect and mechanically mount) the semiconductor chip 30 and thepackage substrate 10. For example, each of the conductive bumps 20 maybe interposed between a bump pad disposed on the semiconductor chip 30and an upper pad disposed on the package substrate 10, such that thebump pad and the upper pad are electrically connected.

The epoxy molding compound 40 may cover the bonded combination of thesemiconductor chip 30 and the package substrate 10. The solder balls 50may be disposed on a lower surface of the package substrate 10, suchthat electrical signal(s) may be communicated (e.g., input to and/oroutput from) the package substrate 10 via the solder balls 50.

Within this configuration, the package substrate 10 may have acoefficient of thermal expansion (hereafter, CTE) greater than a CTE ofthe semiconductor chip 30. As a result, during operation of thesemiconductor package 60, the package substrate 10 may materially expandunder the influence of thermal stress more than the semiconductor chip30. Due to this expansion difference between the semiconductor chip 30and the package substrate 10, mechanical stress may be induced between(e.g.,) at one or more of the conductive bumps 20 and the BEOL of thesemiconductor chip 30. This mechanical stress may causechip-package-interaction (CPI) defects, such as delamination and/orcracking of various layers in the BEOL. Additionally or alternately, ahigh level of structure stress may be generated at an edge of thesemiconductor chip 30.

In some circumstances, stress due to variable rates of thermal expansionbetween the semiconductor chip 30 and the package substrate 10 may beapplied to inner portion(s) of the semiconductor chip 30 through one ormore of the conductive bumps 20, and high levels of stress may beconcentrated around one or more of the conductive bumps 20.Additionally, high levels of stress may be generated at surfaces of themetal wiring in the BEOL adjacent to the conductive bumps 20, as well asan interface portion between the IMD layers in the BEOL. As a result ofone or more of these thermally-induced stress conditions, defects haveconventionally occurred in the interface portions between the IMD layersin the BEOL adjacent to the conductive bumps in certain semiconductorchips. However, embodiments of the inventive concept providesemiconductor chips and semiconductor packages markedly less susceptibleto CPT defects generated in relation to IMD layers in the BEOL.

FIG. 2 is a cross-sectional view illustrating the semiconductor chip 30according to embodiments of the inventive concept, and FIG. 3 is anenlarged view of portion ‘A’ shown in FIG. 2 .

Referring to FIG. 2 , the semiconductor chip 30 includes a FEOL and aBEOL formed on a silicon substrate 100. Here, the silicon substrate 100may be variously positioned in relation to upper and lower portions ofthe semiconductor chip 30.

The FEOL may include various circuits depending on the nature,configuration and operation of the semiconductor chip 30 (e.g., a memorydevice and/or a logic device). In the illustrated example of FIG. 2 ,the FEOL is assumed to include transistors 104, a lower wiring 106, anda lower insulating interlayer 102 formed on the silicon substrate 100.In some embodiments, the FEOL may also include a capacitor.

The BEOL may be disposed on an upper surface of the FEOL and include amultilayer arrangement of metal wirings and IMD layers.

As the BEOL includes multiple metal wirings, each having relatively lowresistance, the IMD layers may include material(s) having a dielectricconstant less than 4 in order to reduced parasitic capacitance betweenthe metal wirings. For example, the IMD layers may include stackedinsulation material layers having different dielectric constants.

Hereinafter, an exemplary IMD layer having a stacked structure will beassumed to include a first IMD layer 200, a second IMD layer 220, athird IMD layer 240, and an uppermost insulation layer 260. However, thenumber and arrangement of stacked forming a IMD layer is a matter ofdesign choice.

In the IMD layer, adjacent layers among the first, second and third IMDlayers 200, 220 and 240, as well as the uppermost insulation layer 260may have different dielectric constants. In addition, the adjacentlayers among the first, second and third IMD layers 200, 220 and 240, aswell as the uppermost insulation layer 260 may have different CTEs.

For example, in some embodiments, the first IMD layer 200 and the thirdIMD layer 240 may include a first low dielectric (low-k) material havinga first dielectric constant. The first low-k material may have a firstCTE. The second IMD layer 220 may include a second low dielectric(low-k) material having a second dielectric constant less than the firstdielectric constant. The second low-k material may have a second CTEdifferent from the first CTE. In this manner, the IMD layer mayalternately stack the first low-k material and the second low-kmaterial. The uppermost insulation layer 260 may have a dielectricconstant different from the dielectric constant of the third IMD layer240, and may have a CTE different from the CTE of the third IMD layer240. The uppermost insulation layer 260 may include silicon oxide havinga dielectric constant that ranges from about 3.9 to about 4.1, and mayinclude (e.g.,) a TEOS (Tetraethyl orthosilicate) material.

For example, the first dielectric material may include a low-k materialhaving a dielectric constant that ranges from between about 2.7 to about3.9. The second dielectric material may include an ultra low-k materialhaving a dielectric constant less than about 2.7. In this case, the CTEof the first IMD layer 200 and the third IMD layer 240 may be about 12ppm, and the CTE of the second IMD layer 220 may be about 14 ppm. Inaddition, the CTE of the uppermost insulation layer 260 may be about 1.5ppm. As such, the adjacent layer among the first to third IMD layers200, 220, and 240 and the uppermost insulation layer 260 may havedifferent CTEs.

A first metal wiring 202 may be formed in the first IMD layer 200, asecond metal wiring 212 may be formed in the second IMD layer 220, andthe third metal wiring 232 may be formed in the third IMD layer 240. Anupper wiring 270 and a metal pad 280 may be formed in the uppermostinsulation layer 260, but at least an upper surface of the metal pad 280may be exposed through the uppermost insulation layer 260.

The first metal wiring 202, the second metal wiring 212, the third metalwiring 232, and the upper wiring 270 may include (e.g.,) copper, and themetal pad 280 may include (e.g.,) aluminum.

A passivation layer 282 may cover the uppermost insulation layer 260 andthe upper surface of the metal pad 280. However, the passivation layer282 may include an opening exposing at least a portion of the metal pad280. A bump pad 284 may be conformally formed on an upper surface of thepassivation layer 282 adjacent to the opening, a sidewall of theopening, and an upper surface of the metal pad 280 exposed by theopening.

A conductive bump 20 may be formed on the bump pad 284. The conductivebump 20 may cover an upper surface of the bump pad 284. Thus, a size ofthe bump pad 284 may be substantially the same as a size of theconductive bump 20.

The first metal wiring 202 may include a first via contact and a firstmetal pattern. The first via contact and the first metal pattern may bestacked in one layer or in a plurality of layers. An uppermost firstmetal pattern may be disposed at an uppermost portion of the first metalwiring 202, and the uppermost first metal pattern may be referred to asa first upper metal pattern 210.

The second metal wiring 212 may include a second via contact and asecond metal pattern. The second via contact and the second metalpattern may be stacked in one layer or a plurality of layers. Anuppermost second metal patterns may be disposed at an uppermost portionof the second metal wiring 212, and the uppermost second metal patternmay be referred to as a second upper metal pattern 230.

The third metal wiring 232 may include a third via contact and a thirdmetal pattern. The third via contact and the third metal pattern may bestacked in one layer or a plurality of layers. An uppermost third metalpatterns may be disposed on an uppermost portion of the third metalwiring 232, and the uppermost third metal pattern may be referred to asa third upper metal pattern 250.

As more particularly illustrated in FIG. 3 , a lower surface of theuppermost insulation layer 260 and an upper surface of the third IMDlayer 240 may come into contact in an area (e.g., an interface portion)between an upper surface and a lower surface of the third upper metalpattern 250. This interface portion between the uppermost insulationlayer 260 and the third IMD layer 240 may be disposed at a heightproximate a sidewall of the third upper metal pattern 250. Hereinafter,the term “interface portion”—as between two adjacent layers (e.g., anupper layer and a lower layer)—includes a lower surface of the upperlayer, an upper surface of the lower layer and a portion between theupper layer and the lower layer. Thus, an “interface portion” comprisesan area of contact between adjacent upper and lower layers and includesat least the lower surface of the upper layer and the upper surface ofthe lower layer.

The interface portion between the uppermost insulation layer 260 and thethird IMD layer 240 may not be coplanar with each of upper and lowersurfaces of the third upper metal pattern 250. Thus, the upper surfaceof the third upper metal pattern 250 may protrude upward from the uppersurface of the third IMD layer 240.

In some embodiments, a third capping layer 254 may be conformally formedon the third IMD layer 240 and an upper surface of the third upper metalpattern 250. The third capping layer 254 may be interposed between theuppermost insulation layer 260 and the third IMD layer 240 and betweenthe uppermost insulation layer 260 and the upper surface of the thirdupper metal pattern 530. The third capping layer 254 may be conformallyformed on the surface of the third upper metal pattern 250 protrudingfrom the upper surface of the third IMD layer 240, such that that thethird capping layer 254 has an uneven shape. The third capping layer 254may include (e.g.,) silicon nitride. The upper wiring 270 may passthrough the third capping layer 254. Thus, the third capping layer 254may not be formed in direct contact with a portion of the third uppermetal pattern 250 and a portion of the upper wiring 270.

As the uppermost insulation layer 260 and the third IMD layer 240 mayinclude materials having different dielectric constants and differentCTEs, a high level of thermally-induced stress may be applied to theinterface portion between the uppermost insulation layer 260 and thethird IMD layer 240. In addition, a high level of thermally-inductedstress may be applied to the upper and lower surfaces of the third uppermetal pattern 250. In particularly, the stress may be concentrated atcorner portions (or edge portions) of the upper and lower surfaces ofthe third upper metal pattern 250. However, as described above, thecorner portions of the upper and lower surfaces of the third upper metalpattern 250 and the interface portion between the uppermost insulationlayer 260 and the third IMD layer 240 are spaced apart from each otherin a vertical direction. Further, the corner portions of the upper andlower surfaces of the third upper metal pattern 250 and the interfaceportions between the uppermost insulation layer 260 and the third MDlayer 240 may not be coplanar with each other. Thus, the stress may beeffectively dispersed, such that high concentrations of the stress arereduced. As a result, a bonding force between the uppermost insulationlayer 260 and the third IMD layer 240 may be increased, and delaminationand/or cracking at the interface portion between the uppermostinsulation layer 260 and the third IMD layer 240 may be reduced.

As described above, the thermally-inducted stress may be highlygenerated around the conductive bump 20. Accordingly, the interfaceportion between the uppermost insulation layer 260 and the third IMDlayer 240 proximate to the conductive bump 20 may vertically displacedto a height between the upper and lower surfaces of the third uppermetal pattern 250 (e.g., at a plane level corresponding to a portionbetween the upper and lower surfaces of the third upper metal pattern250).

In some embodiments, interface portions between the first to third IMDlayers 200, 220 and 240 and the first and second upper metal patterns210 and 230 disposed below the third IMD layer 240 may be disposed in asimilar manner as described above.

In some embodiments, an interface portion between the third IMD layer240 and the second IMD layer 220 may be positioned at a height of aportion between upper and lower surfaces of the second upper metalpattern 230. That is, the interface portion between the third IMD layer240 and the second IMD layer 220 may not be coplanar with each of theupper and lower surfaces of the second upper metal pattern 230. Theupper surface of the second upper metal pattern 230 may protrude fromthe upper surface of the second IMD layer 220. Thus, delamination and/orcracking at the interface portion between the third MD layer 240 and thesecond IMD layer 220 may be reduced.

In some embodiments, an interface portion between the second IMD layer220 and the first IMD layer 200 may be positioned at a height of aportion between upper and lower surfaces of the first upper metalpattern 210. That is, the interface portion between the second IMD layer220 and the first MD layer 200 may not be coplanar with each of theupper and lower surfaces of the first upper metal pattern 210. The uppersurface of the first upper metal pattern 210 may protrude from the uppersurface of the first IMD layer 200. Thus, delamination and/or crackingat the interface portion between second IMD layer 220 and the first IMDlayer 200 may be reduced.

In some embodiments, a second capping layer may be conformally formed onthe second IMD layer 220 and an upper surface of the second upper metalpattern 230. The second capping layer may be interposed between thethird MD layer 240 and the second IMD layer 220 and between the thirdIMD layer 240 and the upper surface of the second upper metal pattern230. In addition, a first capping layer 214 may be conformally formed onthe first IMD layer 200 and an upper surface of the first upper metalpattern 210. The first capping layer 214 may be interposed between thesecond IMD layer 220 and the first IMD layer 200 and between the secondIMD layer 220 and the upper surface of the first upper metal pattern210. Each of the first and second capping layers 214 and 234 may have anuneven shape. Here, one or both of the first and second capping layers214 and 234 may include (e.g.,) silicon nitride.

FIG. 4 is a cross-sectional view illustrating a semiconductor chip inaccordance with embodiments of the inventive concept.

Referring to FIG. 4 , in the semiconductor chip 30, an interface portionbetween the uppermost insulation layer 260 and the third IMD layer 240disposed under the conductive bump 20 may be positioned at a height of aportion between upper and lower surfaces of the third upper metalpattern 250. Thus, the third capping layer 254 between the uppermostinsulation layer 260 and the third IMD layer 240 and the third cappinglayer 254 on an upper surface of the third upper metal pattern 250 maynot be same plane. The third capping layer 254 may have an uneven shape.

However, interface portions between the first, second and third IMDlayers 198, 218 and 240 and upper surfaces of the first and second uppermetal patterns 210 and 230 may be disposed below the third IMD layer 240to be coplanar with each other. In this case, the first and secondcapping layers 214 and 234 may have a flat shape.

In some embodiments, an upper surface of the second IMD layer 218 may becoplanar with the upper surface of the second upper metal pattern 230.

In some embodiments, an upper surface of the first IMD layer 198 may becoplanar with the upper surface of the first upper metal pattern 210.

Alternately, the interface portion between the third IMD layer and thesecond IMD layer may be positioned at a height of a portion between theupper surface and the lower surface of the second upper metal pattern.Also, an upper surface of the first IMD layer under the second IMD layermay be coplanar with the upper surface of the first upper metal pattern.

In this manner, the interface portion between the IMD layers verticallyadjacent to the conductive bump 20—at which a high concentration ofthermally-induced stress is likely to be applied—may be positioned atonly a height of a portion between the upper and lower surfaces of theupper metal pattern. Thus, a bonding force between the IMD layers may beincreased, and stress may be dispersed. As a result, CPI defects, suchas delamination and/or cracking of the IMD layers, may be reduced.

As described above, configurations in which the interface portion of theIMD layers are positioned at a height of the portion between the upperand lower surfaces of the upper metal pattern may be selectively appliedto an entire region or a partial region of the semiconductor chip 30.Hereinafter, the making and use of embodiments of the inventive conceptincluding this type of structure will be described in some additionaldetail.

In FIGS. 6, 7, 8, 9, 10, 11, 12, 13 and 14 , an FEOL may include first,second and/or third capping layers formed on the silicon substrate.However, these material layers are omitted to reduce complexity in thedrawings.

FIG. 5 is a plan (or top down) view and FIG. 6 is a cross-sectional viewtaken along line I-I′ of FIG. 5 that collectively illustrate selectedportions of the semiconductor chip 30 and a conductive bump according toembodiments of the inventive concept.

The semiconductor chip 30 may include a structure wherein an interfaceportion of the constituent IMD layers is positioned at a height of aportion between an upper surface and a lower surface of an upper metalpattern, as described in relation to FIG. 2 . The structure may beapplied to a region proximate to a bump pad (or a region within acertain range from sides of the bump pad).

Referring to FIGS. 5 and 6 , a horizontal width of the bump pad 284associated with the conductive bump 20 is assumed to have a first widthW1. The interface portion of the IMD layers disposed in a first region22 is positioned at a height of a portion between an upper surface and alower surface of an upper metal pattern. The first region 22 may includea region of bump pad 284 and a region within a distance ranging frombetween about 0.5 times to about 1.2 times the first width W1 from thebump pad 284. Here, the first width W1 may be substantially similar to adiameter of the conductive bump 20.

That is, the BEOL in the first region 22 of semiconductor 30 of FIG. 6may have a substantially similar structure to that previously describedin relation to FIG. 2 . In the BEOL in a second region 24 adjacent tothe first region 22, an interface portion of the IMD layers may becoplanar with an upper surface of the upper metal pattern. And in thesecond region 24 proximate to the second region 22, an upper surface ofthe third IMD layer 240 and an upper surface of the third upper metalpattern 250 may be coplanar with each other. In the second region 24, anupper surface of the second IMD layer 220 may be coplanar with an uppersurface of the second upper metal pattern 230. In the second region 22,an upper surface of the first IMD layer 200 may be coplanar with anupper surface of the first upper metal pattern 210.

In some embodiments, consistent with the description of FIG. 4 , in thesemiconductor chip 30, the interface portion between the uppermostinsulation layer 260 and the third IMD layer 240 may be positioned at aheight of a portion between the upper surface and the lower surface ofthe third upper metal pattern 250. An interface portion between the IMDlayers under the third IMD layer 240 may be coplanar with an uppersurface of the upper metal pattern. However, as described with referenceto FIGS. 5 and 6 , the structure may be applied to only the first region22 including a region of the bump pad for forming the conductive bump 20and a region within a defined distance range from the sides of the bumppad.

FIG. 7 is a plan view and FIG. 8 is a cross-sectional view taken alongline II-II′ of FIG. 7 that collectively illustrate selected portions ofthe semiconductor chip 30 and a conductive bump according to embodimentsof the inventive concept.

Here, the semiconductor chip 30 may include a structure in which theinterface portion of the IMD layers is positioned at the height of theportion between the upper surface and the lower surface of the uppermetal pattern, as described in relation to FIG. 2 . However, thestructure may be applied to only an edge region 26 of the semiconductorchip 30.

Referring to FIGS. 7 and 8 , in an edge region 26 of the semiconductorchip 30, the interface portion of the IMD layers may be positioned atthe height of the portion between the upper and lower surfaces of theupper metal pattern. That is, the BEOL in the edge region 26 of thesemiconductor chip 30 may have substantially the same structure asdescribed in relation to FIG. 2 .

At least one conductive bump 20 may be included in the edge region 26 ofthe semiconductor chip 30. As illustrated in FIG. 8 , at least one bumppad 284 may be included in the edge region 26 of the semiconductor chip30.

In contrast, in a more centrally disposed region 28, inwardly proximateto the edge region 26 of the semiconductor chip 30, the interfaceportion of the IMD layers may be coplanar with the upper surface of theupper metal pattern.

In some embodiments, as described in relation to FIG. 4 , in thesemiconductor chip 30, the interface portion between the uppermostinsulation layer 260 and the third IMD layer 240 may be positioned atthe height of the portion between the upper surface and the lowersurface of the third upper metal pattern 250. The interface portionbetween the IMD layers under the third IMD layer 240 may be coplanarwith the upper surface of the upper metal pattern. As described inrelation to FIGS. 7 and 8 , the foregoing structure may be applied toonly the edge region 26 of the semiconductor chip 30.

FIG. 9 is a cross-sectional view illustrating portions of thesemiconductor chip 30 and a conductive bump according to embodiments ofthe inventive concept.

Here, the semiconductor chip 30 may include a structure in which theinterface portion of the IMD layers is positioned at the height of theportion between the upper surface and the lower surface of the uppermetal pattern, as described in relation to FIG. 2 , however, thestructure is applied to the entirety of the semiconductor chip 30.

Referring to FIG. 9 , in the entirety of the semiconductor chip 30, theinterface portion of the IMD layers may be positioned at the height ofthe portion between the upper and lower surfaces of the upper metalpattern.

Thus, in some embodiments like the one described in relation to FIG. 4 ,in the semiconductor chip 30, the interface portion between theuppermost insulation layer 260 and the third IMD layer 240 may bepositioned at the height of the portion between the upper surface andthe lower surface of the third upper metal pattern 250. The interfaceportion between the IMD layers under the third IMD layer 240 may becoplanar with the upper surface of the upper metal pattern. Thestructure may be applied to the entire region of the semiconductor chip30.

FIGS. 10 to 16 are related cross-sectional views illustrating in oneexample a method of manufacturing a semiconductor chip and a conductivebump according to embodiments of the inventive concept. Hereinafter, themethod of manufacturing will be described in the context of thesemiconductor chip described in relation to FIGS. 5 and 6 .

Referring to FIGS. 10 and 11 , circuits constituting memory devices orlogic devices may be formed on a silicon substrate 100, and a lowerinsulating interlayer 102 may be formed to cover the circuits.

A first IMD layer 200 and a first metal wiring 202 may be formed on thelower insulating interlayer 102. In embodiments, the first IMD layer 200may include a first low dielectric material having a first dielectricconstant.

The first metal wiring 202 may be formed by a damascene process. Forexample, the first IMD layer 200 may be formed, and trenches and/or viaholes may be formed in the first IMD layer 200. A metal layer may beformed to fill the trench and/or the via hole, and the first metalwiring 202 may be formed by a planarization process of the metal layer.

The first metal wiring 202 may include a first via contact and a firstmetal pattern. The first via contact and the first metal pattern may bestacked in one layer or in a plurality of layers. An uppermost firstmetal patterns may be disposed at an uppermost portion of the firstmetal wiring 202, and the uppermost first metal pattern may be referredto as a first upper metal pattern 210.

An upper surface of the first IMD layer 200 and an upper surface of thefirst upper metal pattern 210 may be planarized, so that the uppersurfaces of the first IMD layer 200 and the first upper metal pattern210 may be coplanar with each other.

A first photoresist layer may be formed on the first IMD layer 200, andthe first photoresist layer may be formed by exposure and developmentprocesses to form a first photoresist pattern 216.

The first photoresist pattern 216 may include an exposed portion, andthe exposed portion may be positioned at a portion for reducing a heightof an upper surface of the first IMD layer 200.

In some embodiments, as shown in FIG. 10 , the first photoresist pattern216 may be formed to expose a portion around the bump pad 284 forforming the conductive bump 20 in a subsequent process. For example, thefirst photoresist pattern 216 may expose a first region 22 (refer toFIG. 5 ) including a region of bump pad 284 and a region within a rangeof 0.5 times to 1.2 times of a first width from the bump pad 284. Thus,the first photoresist pattern 216 may cover a second region 24 (refer toFIG. 5 ) besides the first region 22.

In some embodiments, as illustrated in FIG. 11 , the first photoresistpattern 216 may be formed to expose an edge region 26 (refer to FIG. 7 )of the semiconductor chip 30. Thus, the first photoresist pattern 216may cover other region 28 (refer to FIG. 7 ) besides the edge region 26of the semiconductor chip 30. In this case, the semiconductor chip asshown in FIG. 8 may be manufactured by subsequent processes.

In some embodiments, the process for forming the first photoresistpattern 216 may not be performed. In this case, the semiconductor chipas shown in FIG. 9 may be manufactured by subsequent processes.

Referring to FIG. 12 , an upper portion of the first IMD layer 200 maybe etched using the first photoresist pattern 216 as an etching mask.The etching process may include, e.g., a wet etching process.

By the etching process, an upper surface of an etched portion of thefirst IMD layer 200 may be positioned at a height of a portion betweenthe upper surface and a lower surface of the first upper metal pattern210. The upper surface of the first IMD layer 200 may not be positionedat the same plane as each of the upper and lower surfaces of the firstupper metal pattern 210. An upper portion of the first IMD layer 200 maybe positioned at a height of a sidewall of the first upper metal pattern210. That is, the upper surface of the first IMD layer 200 exposed bythe first photoresist pattern 216 may be positioned at the height of theportion between the upper surface and the lower surface of the firstupper metal pattern 210.

The first IMD layer 200 covered with the first photoresist pattern 216may not be etched, so that an upper surface of an unetched portion ofthe first IMD layer 200 may be coplanar with the upper surface of thefirst upper metal pattern 210.

Thereafter, as shown in an enlarged drawing, a first capping layer 214may be conformally formed on the surfaces of the first IMD layer 200 andthe first upper metal pattern 210.

Referring to FIG. 13 , a second IMD layer 220 and a second metal wiring212 may be formed on the first IMD layer 200 and the first upper metalpattern 210. In embodiments, the second IMD layer 220 may include asecond low dielectric material having a second dielectric constantdifferent from the first dielectric constant.

The second metal wiring 212 may be formed by a damascene process. Thesecond metal wiring 212 may include a second via contact and a secondmetal pattern. The second via contact and the second metal pattern maybe stacked in one layer or in a plurality of layers. An uppermost secondmetal pattern may be disposed at an uppermost portion of the secondmetal wiring, and the uppermost second metal pattern may be referred toas a second upper metal pattern 230. Upper surfaces of the second IMDlayer 220 and the second upper metal pattern 230 may be coplanar witheach other.

A second photoresist layer may be formed on the second IMD layer 220,and the second photoresist layer may be patterned by exposure anddevelopment processes to form a second photoresist pattern 236.

The second photoresist pattern 236 may include an exposed portion, andthe exposed portion may be positioned at a portion for reducing a heightof an upper surface of the second IMD layer 220.

In some embodiments, as shown in FIG. 13 , the second photoresistpattern 236 may be formed to expose the first region 22 around the bumppad 284 for forming the conductive bump 20 in a subsequent process.

In some embodiments, the second photoresist pattern 236 may be formed toexpose the edge region 26 (refer to FIG. 7 ) of the semiconductor chip30.

In some embodiments, the process of forming the second photoresistpattern 236 may not be performed.

Referring to FIG. 14 , an upper portion of the second IMD layer 220 maybe etched using the second photoresist pattern 236 as an etching mask.The etching process may include, e.g., a wet etching process.

By the etching process, an upper surface of an etched portion of thesecond IMD layer 220 may be positioned at a height of a portion betweenupper and lower surfaces of the second upper metal pattern 230. Theupper surface of the second IMD layer 220 may not be positioned at thesame plane as each of upper and lower surfaces of the second upper metalpattern 230.

That is, the upper surface of the second IMD layer 220 exposed by thesecond photoresist pattern 236 may be positioned at the height of theportion between the upper and lower surfaces of the second upper metalpattern 230.

The second IMD layer 220 covered with the second photoresist pattern 236may not be etched, so that an upper surface of an unetched portion ofthe second IMD layer 220 may be coplanar with the upper surface of thesecond upper metal pattern 230.

Thereafter, as shown in the enlarged drawing, a second capping layer 234may be conformally formed on the surfaces of the second IMD layer 220and the second upper metal pattern 230.

Referring to FIG. 15 , a third IMD layer 240 and a third metal wiring232 may be formed on the second IMD layer 220 and the second upper metalpattern 230. In embodiments, the third IMD layer 240 may include amaterial having a dielectric constant different from the seconddielectric constant. For example, the third IMD layer 240 may include amaterial having the first dielectric constant.

The third metal wiring 232 may be formed by a damascene process. Thethird metal wiring 232 may include a third via contact and a third metalpattern. The third via contact and the third metal pattern may bestacked in one layer or a plurality of layers. An uppermost third metalpattern may be disposed at an uppermost portion of the third metalwiring 232, and the uppermost metal pattern may be referred to as athird upper metal pattern 250. Upper surface of the third IMD layer 240and the third upper metal pattern 250 may be may be coplanar with eachother.

A third photoresist layer may be formed on the third IMD layer 240, andthe third photoresist layer may be patterned by exposure and developmentprocesses to form a third photoresist pattern 256.

The third photoresist pattern 256 may include an exposed portion, andthe exposed portion may be positioned at a portion for reducing a heightof an upper surface of the third IMD layer 240.

In some embodiments, as shown in FIG. 15 , the third photoresist pattern256 may be formed to expose the first region 22 (refer to FIG. 5 )around the bump pad 284 for forming the conductive bump 20 in asubsequent process.

In some embodiments, the third photoresist pattern 256 may be formed toexpose the edge region 26 (refer to FIG. 7 ) of the semiconductor chip30.

In some embodiments, the process of forming the third photoresistpattern 256 may not be performed.

Referring to FIG. 16 , an upper portion of the third IMD layer 240 maybe etched using the third photoresist pattern 256 as an etching mask.The etching process may include, e.g., a wet etching process.

By the etching process, an upper surface of an etched portion of thethird IMD layer 240 may be positioned at a height between upper andlower surfaces of the third upper metal pattern 250. The upper surfaceof the third IMD layer 240 may not be coplanar with each of upper andlower surfaces of the third upper metal pattern 250.

That is, the upper surface of the third IMD layer 240 exposed by thethird photoresist pattern 256 may be positioned at the height of theportion between the upper and lower surfaces of the third upper metalpattern 250.

A portion of the third IMD layer 240 covered with the third photoresistpattern 256 may not be etched by the etching process. Thus, an uppersurface of an unetched portion of the third IMD layer 240 may becoplanar with the upper surface of the third upper metal pattern 250.

Thereafter, as shown in an enlarged drawing, a third capping layer 254may be conformally formed on the surfaces of the third IMD layer 240 andthe third upper metal pattern 250.

Referring to FIG. 6 again, an uppermost insulation layer 260, an upperwiring 270, and a metal pad 280 may be formed on the third IMD layer 240and the third upper metal pattern 250.

The uppermost insulation layer 260 may include an insulating materialhaving a dielectric constant and a CTE different from those of the thirdIMD layer 240. The uppermost insulation layer 260 may include TEOS. Anupper surface of the metal pad 280 may be coplanar with an upper surfaceof the uppermost insulation layer 260.

A passivation layer 282 may be formed on the uppermost insulation layer260 and the metal pad 280. A portion of the passivation layer 282 may beremoved to form an opening exposing the upper surface of the metal pad280. A bump pad 284 may be conformally formed on a portion of thepassivation layer 282, a sidewall of the opening, and an upper surfaceof the metal pad 280 exposed by the opening.

A conductive bump 20 may be formed on a bump pad 284.

By the above described method of manufacturing, the semiconductor chip30 including the conductive bump 20 may be manufactured.

FIG. 17 is a cross-sectional view illustrating portions of asemiconductor chip and a conductive bump according to embodiments of theinventive concept.

The semiconductor chip has a structure characterized by an interfaceportion of the IMD layers disposed at a height of a portion between anupper surface and a lower surface of the upper metal pattern consistentwith the embodiment described in relation to FIG. 2 .

In addition, the semiconductor chip of FIG. 17 suppresses delaminationand/or cracking in a scribe lane at an edge of the semiconductor chip.

Referring to FIG. 17 , the IMD layer stacked structure including aplurality of IMD layers may be formed in the scribe lane, similar to theBEOL of the semiconductor chip 30. A crack prevention structure 290 maybe formed in the IMD layer stacked structure in the scribe lane.

The semiconductor chips 30 may be singulated from the silicon substrate100 by applying a sawing process to the scribe lane of the siliconsubstrate 100. As the scribe lane is sawed, cracking may be generated inthe semiconductor chips 30. Hence, the crack prevention structure 290may be formed in the scribe lane to suppress cracking in thesemiconductor chip 30. Accordingly, the crack prevention structure 290may be included at an edge of the individual semiconductor chip 30.

The crack prevention structure 290 may have a structure in which aplurality of metal wirings are stacked. In some embodiments, the crackprevention structure 290 may include via contacts and stacked metalpatterns having a mesh structure. The via contacts and the metalpatterns included in the crack prevention structure 290 may bepositioned at the same level as the via contacts and the metal patternsincluded in the BEOL of the semiconductor chip 30, respectively.

In a scribe lane including the crack prevention structure 290, aninterface portion of the IMD layers may be positioned at a height of aportion between the upper and lower surfaces of the upper metal pattern.

In some embodiments consistent with the embodiment of FIG. 17 , thecrack prevention structure 290 may include the first, second and thirdmetal wirings 202, 212, and 232 along with the upper wiring 270 in theBEOL arranged in a mesh structure. In the scribe lane in which the crackprevention structure 290 is formed, an interface portion between theuppermost insulation layer 260 and the third IMD layer 240 may bepositioned at a height of a portion between the upper and lower surfacesof the third upper metal pattern 250. In the scribe lane in which thecrack prevention structure 290 is formed, an interface portion betweenthe third IMD layer 240 and the second IMD layer 220 may be positionedat a height of a portion between the upper and lower surfaces of thesecond upper metal pattern 230. In the scribe lane in which the crackprevention structure 290 is formed, an interface portion between thesecond IMD layer 220 and the first IMD layer 200 may be positioned at aheight of a portion between the upper and lower surfaces of the firstupper metal pattern 210.

Thus, in the scribe lane in which the crack prevention structure 290 isformed, a delamination and/or cracking at an interface portion betweenthe IMD layers may be reduced.

FIG. 18 is a cross-sectional view illustrating portions of asemiconductor chip and a conductive bump according to embodiments of theinventive concept, and FIG. 19 is an enlarged view of portion ‘B’ shownin FIG. 18 .

The semiconductor chip and the conductive bump may be substantiallysimilar to those described in relation to FIG. 2 , except for a shape ofan interface portion between IMD layers.

Referring to FIGS. 18 and 19 , an interface portion between theuppermost insulation layer 360 and the third IMD layer 340 may includeconcave portions 342 a and convex portions 342 b.

The concave portions 342 a and the convex portions 342 b may berepeatedly and alternately disposed at an uppermost surface of the thirdIMD layer 340. In addition, the uppermost insulation layer 360 may coverthe third IMD layer 340 to fill the concave portions 342 a of the thirdIMD layer 340. The convex portions 342 b of the third IMD layer 340 maybe coplanar with an upper surface of a third upper metal pattern 350.

In embodiments, as shown in FIG. 19 , a third capping layer 354 may beinterposed between the uppermost insulation layer 360 and the third IMDlayer 340. The third capping layer 354 may be conformally formed on theconcave portions and the convex portions of the third IMD layer 340.

The uppermost insulation layer 360 may have a material having adielectric constant and a CTE different from those of the third IMDlayer 340. A stress may be highly applied to adjacent the uppermostinsulation layer 360 and the third IMD layer 340. However, the interfaceportion between the uppermost insulation layer 360 and the third IMDlayer 340 may have the concave portions and the convex portions, so thata contact area between the uppermost insulation layer 360 and the thirdIMD layer 340 may be increased. Thus, a bonding force between theuppermost insulation layer 360 and the third IMD layer 340 may beincreased, such that delamination and/or cracking at the interfaceportion between the uppermost insulation layer 360 and the third IMDlayer 340 may be reduced.

As described above, the stress may be highly generated at around theconductive bump 20. Thus, the interface portion between the uppermostinsulation layer 360 and the third IMD layer 340 under the conductivebump 20 may have the concave portions and the convex portions.

In some embodiments, the concave portions and the convex portions may befurther disposed at the interface portion of the IMD layers 300 and 320under the third IMD layer 340.

In some embodiments, the concave portions 332 a and the convex portions332 b may be included at an interface portion between the third IMDlayer 340 and the second IMD layer 320. Thus, delamination and/orcracking at an interface portion between the third IMD layer 340 and thesecond IMD layer 320 may be reduced. A second capping layer may beconformally formed on the concave portions and the convex portions of anupper surface of the second IMD layer 320.

In some embodiments, the concave portions 302 a and the convex portions302 b may be included at an interface portion between the second IMDlayer 320 and the first IMD layer 300. Thus, delamination and/orcracking at an interface portion between the second IMD layer 320 andthe first IMD layer 300 may be decreased. A first capping layer may beconformally formed on the concave portions and the convex portions of anupper surface of the first IMD layer 300.

In some embodiments, the semiconductor chip 30 may include a structurein which the concave portions and the convex portions are formed at aninterface portion of the IMD layers, the same as illustrated withreference to FIG. 18 , and the structure may be applied to the firstregion.

In some embodiments, the semiconductor chip 30 may include a structurein which the concave portions and the convex portions are formed at aninterface portion of the IMD layers, the same as illustrated withreference to FIG. 18 , and the structure may be only applied to the edgeregion of the semiconductor chip 30.

In some embodiments, the semiconductor chip 30 may include a structurein which the concave portions and the convex portions are formed at aninterface portion of the IMD layers, the same as illustrated withreference to FIG. 18 , and the structure may be applied to the entireregion of the semiconductor chip 30.

The semiconductor chip and the conductive bump shown in FIG. 18 may bemanufactured by processes similar to that illustrated with reference toFIGS. 10 to 16 .

However, exposed portions of each of the first to third photoresistpatterns may be different from those of the first to third photoresistpatterns illustrated with reference to FIGS. 10 to 16 . That is, theexposed portion of the first photoresist pattern may be positioned at aportion corresponding to the concave portion of the first IMD layer 200.The exposed portion of the second photoresist pattern may be positionedat a portion corresponding to the concave portion of the second IMDlayer 220. The exposed portion of the third photoresist pattern may bepositioned at a portion corresponding to the concave portion of thethird IMD layer 240.

In embodiments, a bonding force between the IMD layers may be increased,and thermally-induced stress may be decreased at the interface portionbetween the IMD layers. Thus, CPI defects due to differences in rates ofthermal expansion between the package substrate and the semiconductorchip may be reduced.

The foregoing embodiments ac illustrative of the inventive concept whichshould not be construed as being limited thereto. Although a fewembodiments have been described, those skilled in the art will readilyappreciate that many modifications are possible in the embodimentswithout materially departing from the novel teachings and advantages ofthe inventive concept. Accordingly, all such modifications are intendedto be included within the scope of the present inventive concept asdefined in the claims.

What is claimed is:
 1. A semiconductor chip comprising: an intermetaldielectric (IMD) layer on a substrate; an uppermost insulation layer onthe IMD layer, the uppermost insulation layer having a dielectricconstant different from a dielectric constant of the IMD layer; a metalwiring in the IMD layer, the metal wiring including a via contact and ametal pattern; a metal pad in the uppermost insulation layer, the metalpad being electrically connected to the metal wiring; and a bump pad onthe metal pad, wherein: at least a portion of the IMD layer extends to aheight of an upper surface of the metal pattern, at least a portion ofthe uppermost insulation layer extends to a lower height than the uppersurface of the metal pattern but not the lower surface of the metalpattern, and an interface portion between the uppermost insulation layerand the IMD layer is positioned at a level of a sidewall of the metalpattern.
 2. The semiconductor chip of claim 1, wherein the upper surfaceof the metal pattern is exposed through an upper surface of the IMDlayer.
 3. The semiconductor chip of claim 1, wherein the IMD layerincludes an oxide having a dielectric constant less than
 4. 4. Thesemiconductor chip of claim 1, wherein the uppermost insulation layerincludes an oxide having a dielectric constant greater than a dielectricconstant of the IMD layer.
 5. The semiconductor chip of claim 1, whereinthe IMD layer has a coefficient of thermal expansion different from acoefficient of thermal expansion of the uppermost insulation layer. 6.The semiconductor chip of claim 1, further comprising a conductive bumpon the bump pad.
 7. The semiconductor chip of claim 1, furthercomprising: a first region in which the bump pad is formed, wherein aportion between the upper surface and the lower surface of the metalpattern in the IMD layer is disposed at a distance a ranging from about0.5 times to about 1.2 times a width of the bump pad from the bump pad.8. The semiconductor chip of claim 7, wherein the first region is anedge region of the substrate.
 9. The semiconductor chip of claim 1,further comprising: a capping layer conformally formed between the IMDlayer and the uppermost insulation layer, wherein an upper surface ofthe metal pattern is exposed through an upper surface of the IMD layer.10. The semiconductor chip of claim 1, further comprising: a stackedplurality of IMD layers disposed between the substrate and the IMDlayer; and a plurality of metal wirings in each one of the stackedplurality of IMD layers, wherein adjacent IMD layers among the stackedplurality of IMD layers have different dielectric constants.
 11. Thesemiconductor chip of claim 10, wherein an interface portion is disposedat a height between an upper surface and a lower surface of the metalpattern in an IMD layer among the plurality of IMD layers.
 12. Asemiconductor chip comprising: a first intermetal dielectric (IMD) layeron a substrate, the first IMD layer having a first dielectric constant;a second IMD layer on the first IMD layer, the second IMD layer having asecond dielectric constant different from the first dielectric constant;a third IMD layer on the second IMD layer, the third IMD layer having athird dielectric constant different from the second dielectric constant;an uppermost insulation layer on the third IMD layer, the uppermostinsulation layer having a fourth dielectric constant different from thethird dielectric constant; a first metal wiring in the first IMD layer,the first metal wiring including a first via contact and a first metalpattern; a second metal wiring in the second IMD layer, the second metalwiring including a second via contact and a second metal pattern; athird metal wiring in the third IMD layer, the third metal wiringincluding a third via contact and a third metal pattern; a metal pad inthe uppermost insulation layer, the metal pad being electricallyconnected to the third metal wiring; and a bump pad for forming aconductive bump on the metal pad, wherein: at least a portion of thethird IMD layer extends to a height of an upper surface of the thirdmetal pattern, at least a portion of the uppermost insulation layerextends to a lower height than the upper surface of the third metalpattern but not the lower surface of the third metal pattern, and aninterface portion between the uppermost insulation layer and the thirdIMD layer is positioned at a level of a sidewall of the third metalpattern.
 13. The semiconductor chip of claim 12, wherein: in a firstregion, an upper surface of the second metal pattern disposed at anuppermost portion is exposed through an upper surface of the second IMDlayer, and in the first region, an upper surface of the first metalpattern disposed at an uppermost portion is exposed through an uppersurface of the first IMD layer.
 14. The semiconductor chip of claim 12,wherein: the first dielectric constant, the second dielectric constantand the third dielectric constant are less than 4, and the fourthdielectric constant is greater than the first dielectric constant, thesecond dielectric constant and the third dielectric constant.
 15. Thesemiconductor chip of claim 12, wherein among in the first IMD layer,the second IMD layer, the third IMD layer and the uppermost insulationlayer, adjacent layers have different coefficients of thermal expansion.16. The semiconductor chip of claim 12, wherein a first region includesa region including the bump pad and a region within a distance rangingfrom between about 0.5 times to about 1.2 times a width of the bump padfrom the bump pad.
 17. The semiconductor chip of claim 12, wherein: afirst region is an edge region of the substrate, and at least one bumppad is disposed in the edge region.
 18. The semiconductor chip of claim12, further comprising: a first capping layer conformally formed on aportion between the first IMD layer and the second IMD layer and asurface of the first metal pattern; a second capping layer conformallyformed on a portion between the second IMD layer and the third IMD layerand a surface of the second metal pattern; and a third capping layerconformally formed on a portion between the third IMD layer and theuppermost insulation layer and a surface of the third metal patternprotruding from an upper surface of the third IMD layer.
 19. Asemiconductor package comprising: a package substrate; a semiconductorchip; and conductive bumps interposed between the package substrate andthe semiconductor chip and electrically connecting the semiconductorchip and the package substrate, wherein: the semiconductor chipincludes: an intermetal dielectric (IMD) layer on a substrate; anuppermost insulation layer contacting an upper surface of the IMD layer,the uppermost insulation layer having a dielectric constant differentfrom a dielectric constant of the IMD layer; a metal wiring in the IMDlayer, the metal wiring including a via contact and a metal pattern; ametal pad in the uppermost insulation layer, the metal pad beingelectrically connected to the metal wiring; and a bump pad on the metalpad, at least a portion of the IMD layer extends to a height of an uppersurface of the metal pattern, at least a portion of the uppermostinsulation layer extends to a lower height than the upper surface butnot the lower surface of the metal pattern, and an interface portionbetween the uppermost insulation layer and the IMD layer is positionedat a level of a sidewall of the metal pattern.
 20. The semiconductorpackage of claim 19, wherein the IMD layer and the uppermost insulationlayer in the semiconductor chip have different coefficients of thermalexpansion.